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1/19 preliminary data may 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m95040 M95020, m95010 4/2/1 kbit serial spi bus eeprom with high speed clock n compatible with spi bus serial interface (positive clock spi modes) n single supply voltage: C 4.5v to 5.5v for m950x0 C 2.5v to 5.5v for m950x0-w C 1.8v to 3.6v for m950x0-r n 5 mhz clock rate (maximum) n status register n byte and page write (up to 16 bytes) n self-timed programming cycle n adjustable size read-only eeprom area n enhanced esd protection n more than 1,000,000 erase/write cycles n more than 40 year data retention description these spi-compatible electrically erasable programmable memory (eeprom) devices are organized as 512 x 8 bits, 256 x 8 bits and 128 x 8 bits (m95040, M95020, m95010). they operate down to 2.5 v (for the -w version of each device), and down to 1.8 v (for the -r version of each device). figure 1. logic diagram ai01789c s v cc m95xxx hold v ss w q c d table 1. signal names c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground psdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop8 (dw) 169 mil width 8 1 8 1 8 1
m95040, M95020, m95010 2/19 the m95040 and M95020, m95010 are available in plastic dual-in-line, plastic small outline and thin shrink small outline packages. each memory device is accessed by a simple serial interface that is spi-compatible. the bus signals are c, d and q, as shown in table 1 and figure 3. the device is selected when the chip select input (s ) is held low. communications with the chip can be interrupted using the hold input (hold ). write operations are disabled by the write protect input (w ). signal description serial output (q) the output pin is used to transfer data serially out of the memory. data is shifted out on the falling edge of the serial clock. serial input (d) the input pin is used to transfer data serially into the device. instructions, addresses, and the data to be written, are each received this way. input is latched on the rising edge of the serial clock. serial clock (c) the serial clock provides the timing for the serial interface (as shown in figure 4). instructions, addresses, or data are latched, from the input pin, figure 2a. dip connections d v ss c hold q sv cc w ai01790c m95xxx 1 2 3 4 8 7 6 5 figure 2b. so and tssop connections 1 ai01791c 2 3 4 8 7 6 5 d v ss c hold q sv cc w m95xxx table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) 3. eiaj ic-121 (condition c) (200pf, 0w). symbol parameter value unit t a ambient operating temperature -40 to 125 c t stg storage temperature -65 to 150 c t lead lead temperature during soldering psdip8: 10 sec so8: 40 sec tssop8: t.b.c. 260 215 t.b.c. c v o output voltage range -0.3 to v cc +0.6 v v i input voltage range -0.3 to 6.5 v v cc supply voltage range -0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 2 4000 v electrostatic discharge voltage (machine model) 3 400 v
3/19 m95040, M95020, m95010 on the rising edge of the clock input. the output data on the q pin changes state after the falling edge of the clock input. chip select (s ) when s is high, the memory device is deselected, and the q output pin is held in its high impedance state. unless an internal write operation is underway, the memory device is placed in its stand-by power mode. after power-on, a high-to-low transition on s is required prior to the start of any operation. write protect (w ) this pin is for hardware write protection. when w is low, writes to the device are disabled, but all other operations remain enabled. when w is high, write operations are enabled. if w goes low at any time before the last bit, d0, of the data stream, the write enable latch is reset, thus preventing the write from taking effect. no action on w or on the write enable latch can interrupt a write cycle which has commenced, though. hold (hold ) the hold pin is used to pause the serial communications between the spi memory and controller, without losing bits that have already been decoded in the serial sequence. for a hold condition to occur, the memory device must already have been selected (s = 0). the hold condition starts when the hold pin is held low while the clock pin (c) is also low (as shown in figure 14). during the hold condition, the q output pin is held in its high impedance state, and the levels on the input pins (d and c) are ignored by the memory device. it is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. the memory remains in the hold state as long as the hold pin is low. to restart communication with the device, it is necessary both to remove the hold condition (by taking hold high) and to select the memory (by taking s low). the memory can be driven by a microcontroller with its spi peripheral running in either of the two following modes: (cpol, cpha) = (0,0) or (cpol,cpha) = (1,1). for these two modes, input data is latched in by the low to high transition of clock c, and output data is available from the high to low transition of clock (c). the difference between (cpol, cpha) = (0, 0) and (cpol, cpha) = (1, 1) is the stand-by polarity: c remains at 0 for (cpol, cpha) = (0, 0) and c remains at 1 for (cpol, cpha) = (1, 1) when there is no data transfer. operations all instructions, addresses and data are shifted serially in and out of the chip. the most significant bit is presented first, with the data input (d) sampled on the first rising edge of the clock (c) after the chip select (s ) goes low. figure 3. microcontroller and memory devices on the spi bus ai01958c master (st6, st7, st9, st10, others) m95xxx sdo sdi sck cqd s m95xxx cqd s m95xxx cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = ('0', '0') or ('1', '1')
m95040, M95020, m95010 4/19 every instruction starts with a single-byte code, as summarized in table 3. this code is entered via the data input (d), and latched on the rising edge of the clock input (c). to enter an instruction code, the product must have been previously selected (s held low). if an invalid instruction is sent (one not contained in table 3), the chip automatically deselects itself. write enable (wren) and write disable (wrdi) the write enable latch, inside the memory device, must be set prior to each write and wrsr operation. the wren instruction (write enable) sets this latch, and the wrdi instruction (write disable) resets it. the latch becomes reset by any of the following events: C power on C wrdi instruction completion C wrsr instruction completion C write instruction completion C the w pin is held low. as soon as the wren or wrdi instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected. read status register (rdsr) the rdsr instruction allows the status register to be read, and can be sent at any time, even during a write operation. indeed, when a write is in progress, it is recommended that the value of the write-in-progress (wip) bit be checked. the value in the wip bit (whose position in the status register is shown in table 4) can be polled, before sending a new write instruction. the write-in-process (wip) bit is read-only, and indicates whether the memory is busy with a write operation. a 1 indicates that a write is in progress, and a 0 that no write is in progress. the write enable latch (wel) bit indicates the status of the write enable latch. it, too, is read-only. its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing wren or wrdi instruction. it cannot be changed using a wrsr instruction. a 1 indicates that the latch is set (the forthcoming write instruction will be executed), and a 0 that it is reset (and any forthcoming write instructions will be ignored). the block protect (bp0 and bp1) bits indicate the amount of the memory that is to be write- protected. these two bits are non-volatile. they are set using a wrsr instruction. figure 4. data and clock timing ai01438 c c msb lsb cpha d or q 0 1 cpol 0 1 table 3. instruction set note: 1. a8 = 1 for the upper page on the m95040, and 0 for the lower page, and is dont care for other devices. 2. x = dont care. table 4. status register format note: 1. bp1 and bp0 are read and write bits. 2. wel and wip are read only bits. 3. b7 to b4 are read only bits. instruc tion description instruction format wren set write enable latch 0000 x110 wrdi reset write enable latch 0000 x100 rdsr read status register 0000 x101 wrsr write status register 0000 x001 read read data from memory array 0000 a 8 011 write write data to memory array 0000 a 8 010 b7 b0 1 1 1 1 bp1 bp0 wel wip
5/19 m95040, M95020, m95010 figure 5. rdsr: read status register sequence figure 6. block diagram c d s 2 1 3456789101112131415 instruction 0 ai01444 q 7 6543210 status reg. out high impedance msb ai01272b hold s w control logic high voltage generator i/o shift register address register and counter data register 16 bytes x decoder y decoder c d q size of the read only eeprom area status register
m95040, M95020, m95010 6/19 during a write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read using the rdsr instruction. however, during a write operation, the values of the non-volatile bits (bp0, bp1) become frozen at a constant value. the updated value of these bits becomes available when a new rdsr instruction is executed, after completion of the write cycle. on the other hand, the two read-only bits (wel, wip) are dynamically updated during internal write cycles. using this facility, it is possible to poll the wip bit to detect the end of the internal write cycle. write status register (wrsr) the format of the wrsr instruction is shown in figure 7. after the instruction and the eight bits of the status register have been latched-in, the internal write cycle is triggered by the rising edge of the s line. this must occur after the falling edge of the 16 th clock pulse, and before the rising edge of the 17 th clock (as indicated in figure 7), otherwise the internal write sequence is not performed. the wrsr instruction is used to select the size of memory area that is to be write-protected. the bp1 and bp0 bits of the status register have the appropriate value (see table 5) written into them after the contents of the protected area of the eeprom have been written. the initial delivery state of the bp1 and bp0 bits is 00, indicating a write-protection size of 0. read operation the chip is first selected by holding s low. the serial one byte read instruction is followed by a one byte address (a7-a0), each bit being latched- in during the rising edge of the clock (c). the most significant bit, a8, of the address is incorporated as bit b3 of the instruction byte, as shown in table 3. the data stored in the memory, at the selected address, is shifted out on the q output pin. each bit is shifted out during the falling edge of the clock (c) as shown in figure 8. the internal address counter is automatically incremented to the next higher address after each byte of data has been shifted out. the data stored in the memory, at the next address, can be read by successive clock pulses. when the highest address is reached, the address counter rolls over to 0000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by deselecting the chip. table 5. write protected block size status register bits protected block array addresses protected bp1 bp0 m95040 M95020 m95010 0 0 none none none none 0 1 upper quarter 180h - 1ffh c0h - ffh 060h - 7fh 1 0 upper half 100h - 1ffh 80h - ffh 040h - 7fh 1 1 whole memory 000h - 1ffh 00h - ffh 000h - 7fh figure 7. wrsr: write status register sequence c d ai01445 s q 2 1 3456789101112131415 high impedance instruction status reg. 0
7/19 m95040, M95020, m95010 the chip can be deselected at any time during data output. if a read instruction is received during a write cycle, it is rejected, and the memory device deselects itself. byte write operation before any write can take place, the wel bit must be set, using the wren instruction. the write state is entered by selecting the chip, issuing two bytes of instruction and address, and one byte of data. chip select (s ) must remain low throughout the operation, as shown in figure 10. the product must be deselected just after the eighth bit of the data byte has been latched in, as shown in figure 10, otherwise the write process is cancelled. as soon as the memory device is deselected, the self- timed internal write cycle is initiated. while the write is in progress, the status register may be read to check the status of the bp1, bp0, wel and wip bits. in particular, wip contains a 1 during the self-timed write cycle, and a 0 when the cycle is complete, (at which point the write enable latch is also reset). page write operation a maximum of 16 bytes of data can be written during one write time, t w , provided that they are all to the same page (see figure 6). the page write operation is the same as the byte write operation, except that instead of deselecting the device after the first byte of data, up to 15 additional bytes can be shifted in (and then the device is deselected after the last byte). any address of the memory can be chosen as the first address to be written. if the address counter reaches the end of the page (an address of the figure 8. read eeprom array operation sequence note: 1. depending on the memory size, as shown in table 6, the most significant address bits are dont care. c d ai01440 s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 23 76543 2 0 1 high impedance data out instruction byte address 0 table 6. address range bits device m95040 M95020 m95010 address bits a8-a0 a7-a0 a6-a0 figure 9. write enable latch sequence c d ai01441 s q 2 1 34567 high impedance 0
m95040, M95020, m95010 8/19 figure 10. byte write operation sequence note: 1. depending on the memory size, as shown in table 6, the most significant address bits are dont care. ai01442 c d s q a7 2 1 345678910111213141516171819 a6 a5 a4 a3 a2 a1 a0 a8 20 21 22 23 high impedance instruction byte address 0 765432 0 1 data byte figure 11. page write operation sequence note: 1. depending on the memory size, as shown in table 6, the most significant address bits are dont care. c d s 2 1 345678910111213141516171819 20 21 22 23 instruction byte address 0 data byte 1 c d ai01443 s 26 25 27 28 29 30 31 8+8n 24 data byte 16 9+8n 10+8n 11+8n 12+8n 13+8n 14+8n 15+8n 136 137 138 139 140 141 142 143 data byte n 76 3210 54 data byte 2 7 a7 a6 a5 a4 a3 a2 a1 a0 a8 765432 0 1 7 6543210765432 0 1
9/19 m95040, M95020, m95010 form xxxx 1111) and the clock continues, the counter rolls over to the first address of the same page (xxxx 0000) and over-writes any previously written data. as before, the write cycle only starts if the s transition occurs just after the eighth bit of the last data byte has been received, as shown in figure 11. data protection and protocol safety to protect the data in the memory from inadvertent corruption, the memory device only responds to correctly formulated commands. the main security measures can be summarized as follows: C the wel bit is reset at power-up. Cs must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). C accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. C after execution of a wren, wrdi, or rdsr instruction, the chip enters a wait state, and waits to be deselected. C invalid s and hold transitions are ignored. power on state after power-on, the memory device is in the following state: C low power stand-by state C deselected (after power-on, a high-to-low transition is required on the s input before any operations can be started). C not in the hold condition C the wel bit is reset C the bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). initial delivery state the device is delivered with the memory array in a fully erased state (all data set at all 1s or ffh). the status register bits are initialized to 00h, as shown in table 7. table 7. initial status register format b7 b0 1 1110000 table 8. input parameters 1 (t a = 25 c, f = 5 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c out output capacitance (q) 8 pf c in input capacitance (d) 8 pf input capacitance (other pins) 6 pf
m95040, M95020, m95010 10/19 table 9. dc characteristics (t a = C40 to 85 c or C40 to 125 c; v cc = 4.5 to 5.5 v) (t a = C40 to 85 c; v cc = 2.5 to 5.5 v) (t a = C20 to 85 c; v cc = 1.8 to 3.6 v) note: 1. for all 5v range devices, the device meets the output requirements for both ttl and cmos standards. symbol parameter voltage range temp. range test condition min. max. unit i li input leakage current all all 2 a i lo output leakage current all all 2 a i cc supply current 4.5-5.5 6 c = 0.1v cc /0.9v cc , at 5 mhz, v cc = 5 v, q = open 5ma 4.5-5.5 3 c = 0.1v cc /0.9v cc , at 2 mhz, v cc = 5 v, q = open 5ma 2.5-5.5 6 c = 0.1v cc /0.9v cc , at 2 mhz, v cc = 2.5 v, q = open 2ma 1.8-3.6 5 c = 0.1v cc /0.9v cc , at 1 mhz, v cc = 1.8 v, q = open 2ma i cc1 supply current (stand-by) 4.5-5.5 6 s = v cc , v in = v ss or v cc , v cc = 5 v 10 a 4.5-5.5 3 s = v cc , v in = v ss or v cc , v cc = 5 v 10 a 2.5-5.5 6 s = v cc , v in = v ss or v cc , v cc = 2.5 v 2a 1.8-3.6 5 s = v cc , v in = v ss or v cc , v cc = 1.8 v 2 a v il input low voltage all all C 0.3 0.3 v cc v v ih input high voltage all all 0.7 v cc v cc +1 v v ol 1 output low voltage 4.5-5.5 6 i ol = 2 ma, v cc = 5 v 0.4 v 4.5-5.5 3 i ol = 2 ma, v cc = 5 v 0.4 v 2.5-5.5 6 i ol = 1.5 ma, v cc = 2.5 v 0.4 v 1.8-3.6 5 i ol = 0.15 ma, v cc = 1.8 v 0.3 v v oh 1 output high voltage 4.5-5.5 6 i oh = C2 ma, v cc = 5 v 0.8 v cc v 4.5-5.5 3 i oh = C2 ma, v cc = 5 v 0.8 v cc v 2.5-5.5 6 i oh = C0.4 ma, v cc = 2.5 v 0.8 v cc v 1.8-3.6 5 i oh = C0.1 ma, v cc = 1.8 v 0.8 v cc v
11/19 m95040, M95020, m95010 table 10a. ac characteristics note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. symbol alt. parameter m95040, M95020, m95010 unit v cc =4.5 to 5.5 v t a =C40 to 85c v cc =4.5 to 5.5 v t a =C40 to 125c min max min max f c f sck clock frequency d.c. 5 d.c. 2 mhz t slch t css1 s active setup time 90 200 ns t shch t css2 s not active setup time 90 200 ns t shsl t cs s deselect time 100 200 ns t chsh t csh s active hold time 90 200 ns t chsl s not active hold time 90 200 ns t ch 1 t clh clock high time 90 200 ns t cl 1 t cll clock low time 90 200 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 20 40 ns t chdx t dh data in hold time 30 50 ns t dldh 2 t ri data in rise time 1 1 s t dhdl 2 t fi data in fall time 1 1 s t hhch t cd clock low hold time after hold not active 70 140 ns t hlch clock low hold time after hold active 40 90 ns t clhl clock low set-up time before hold active 0 0 ns t clhh clock low set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 100 250 ns t clqv t v clock low to output valid 60 150 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 50 100 ns t qhql 2 t fo output fall time 50 100 ns t hhqx 2 t lz hold high to output low-z 50 100 ns t hlqz 2 t hz hold low to output high-z 100 250 ns t w t wc write time 10 10 ms
m95040, M95020, m95010 12/19 table 10b. ac characteristics note: 1. t ch + t cl 3 1 / f c . 2. value guaranteed by characterization, not 100% tested in production. symbol alt. parameter m950x0-w m950x0-r unit v cc =2.5 to 5.5 v t a =C40 to 85c v cc =1.8 to 3.6 v t a =C20 to 85c min max min max f c f sck clock frequency d.c. 2 d.c. 1 mhz t slch t css1 s active setup time 200 400 ns t shch t css2 s not active setup time 200 400 ns t shsl t cs s deselect time 200 300 ns t chsh t csh s active hold time 200 400 ns t chsl s not active hold time 200 400 ns t ch 1 t clh clock high time 200 400 ns t cl 1 t cll clock low time 200 400 ns t clch 2 t rc clock rise time 1 1 s t chcl 2 t fc clock fall time 1 1 s t dvch t dsu data in setup time 40 60 ns t chdx t dh data in hold time 50 100 ns t dldh 2 t ri data in rise time 1 1 s t dhdl 2 t fi data in fall time 1 1 s t hhch t cd clock low hold time after hold not active 140 350 ns t hlch clock low hold time after hold active 90 200 ns t clhl clock low set-up time before hold active 0 0 ns t clhh clock low set-up time before hold not active 0 0 ns t shqz 2 t dis output disable time 250 500 ns t clqv t v clock low to output valid 150 380 ns t clqx t ho output hold time 0 0 ns t qlqh 2 t ro output rise time 100 200 ns t qhql 2 t fo output fall time 100 200 ns t hhqx 2 t lz hold high to output low-z 100 250 ns t hlqz 2 t hz hold low to output high-z 250 500 ns t w t wc write time 10 10 ms
13/19 m95040, M95020, m95010 figure 13. serial input timing figure 14. hold timing c d ai01447 s msb in q tdvch high impedance lsb in tslch tchdx tdldh tdhdl tchcl tclch tshch tshsl tchsh tchsl c q ai01448 s d hold tclhl thlch thhch tclhh thhqx thlqz figure 12. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc table 11. ac measurement conditions note: 1. output hi-z is defined as the point where data is no long- er driven. input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc output load c l = 100 pf
m95040, M95020, m95010 14/19 figure 15. output timing c q ai01449b s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv table 12. ordering information scheme note: 1. temperature range available only on request, in v cc range 4.5 v to 5.5 v only. 2. the -r version (v cc range 1.8 v to 3.6 v) only available in temperature range 5. 3. all devices use a positive clock strobe: data in is strobed on the rising edge of the clock (c) and data out is synchronized from the falling edge of the clock. example: m95040 C w mn 6 tr memory capacity 3 option 040 4 kbit (512 x 8) with positive clock strobe tr tape and reel packing 020 2 kbit (256 x 8) with positive clock strobe 010 1 kbit (128 x 8) with positive clock strobe temperature range 5 C20 c to 85 c 6 C40 c to 85 c 3 1 C40 c to 125 c operating voltage package blank 4.5 v to 5.5 v bn psdip8 (0.25 mm frame) w 2.5 v to 5.5 v mn so8 (150 mil width) r 2 1.8 v to 3.6 v dw tssop8 (169 mil width) ordering information the notation used for the device number is as shown in table 12. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you.
15/19 m95040, M95020, m95010 figure 16. psdip8 (bn) note: 1. drawing is not to scale. psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b table 13. psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame symb. mm inches typ. min. max. typ. min. max. a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb 10.00 0.394 l 3.00 3.80 0.118 0.150 n8 8
m95040, M95020, m95010 16/19 table 14. so8 - 8 lead plastic small outline, 150 mils body width symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 figure 17. so8 narrow (mn) note: 1. drawing is not to scale. so-a e n cp b e a d c l a1 a 1 h h x 45?
17/19 m95040, M95020, m95010 figure 18. tssop8 (dw) note: 1. drawing is not to scale. tssop 1 n cp n/2 die c l a1 e e1 d a2 a a e b table 15. tssop8 - 8 lead thin shrink small outline symb. mm inches typ. min. max. typ. min. max. a 1.10 0.043 a1 0.05 0.15 0.002 0.006 a2 0.85 0.95 0.033 0.037 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e 6.25 6.50 0.246 0.256 e1 4.30 4.50 0.169 0.177 e 0.65 C C 0.026 C C l 0.50 0.70 0.020 0.028 a 0 8 0 8 n8 8 cp 0.08 0.003
m95040, M95020, m95010 18/19 table 16. revision history date description of revision 10-may-2000 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the byte write operation
19/19 m95040, M95020, m95010 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sing apore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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